Interrupt Instructions

INTERRUPT INSTRUCTIONS: The Enable Interrupts (EI) and Disable Interrupts (DI) instructions allow the MP to permit or deny interrupts under program control. For the EI, the interrupts will be enabled following the completion of the next instruction following the EI. This allows at least one more instruction, perhaps a RET or JMP, to be executed before the MP allows itself to again be interrupted. For the DI, the interrupts are disabled immediately. No flags are affected.
HALT and NO-OP: The Halt (HLT) and No-Operation (NOP) instructions serve general utility purposes. The Halt will stop the processor from further execution; it can be restarted again only by an interrupt. A reset signal applied to the MP will abort the Halt. The MP may enter a Hold state, as the result of another device wanting the bus, from a Halt, but will return to the Halt state when the Hold is canceled. The NOP is simply a one-byte long place holder, which is passed through automatically without any data motion or action of any kind. It is used primarily as a programmer’s aid in saving space within language programs for later use.
The Read Interrupt Mask (RIM) and Set Interrupt Mask (SIM) instructions are used to service both the extended interrupt system of the ‘85 and the Serial Input Data (SID) and Serial Output Data (SOD) pins on the device. While these items are both serviced by the same instructions, they are not electrically or logically related, and should not be confused. The Interrupt Mask is a group of bits which can be accessed by these two instructions via the accumulator. A discussion of the two instructions follows.
READ INTERRUPT MASK (RIM): This instruction permits the system to examine the interrupt mask by loading into the A register a byte which defines the condition of the mask bits for the maskable interrupts, the condition of the interrupts pending for the maskable interrupts, the condition of the Interrupt Enable flag, and the condition of the Serial Input Data (SID) pin on the MP. The format is:
D7
D6
D5
D4
D3
D2
D1
D0
SID
I7.5
I6.5
I5.5
IE
M7.5
M6.5
M5.5
From the D0 end of the byte, the purpose of these bits are as follows:
INTERRUPT MASK BITS D0, D1, D2: These bits indicate whether the interrupts for vectors 5.5, 6.5, and 7.5 are masked on or off. The bits are set to a 1 for disabled, and 0 for enabled. These bits allow the program to examine the mask and obtain the current status of it. It is a valuable tool, since one program section may not necessarily know what a second section is doing or expecting.
INTERRUPT ENABLE BIT D3: This bit corresponds to the Interrupts Enabled, flip-flop in the 8080. It is set or reset by the Enable Interrupts or Disable Interrupts OP codes in the same manner as in the 8080. The interrupts involved are the standard 8 vectored interrupts, and it has no effect on those special to the 8085. However, in the case of a Trap interrupt (unmaskable), the status of bit 3 may be lost, so that Intel suggests that a RIM be executed as part of the Trap service routine to preserve the condition of the Interrupts Enabled flag prior to the occurrence of Trap. The flag is not affected by the other special interrupts.
INTERRUPTS PENDING BITS D4, D5, D6: These bits indicate what interrupts have occurred since the last time that specific interrupt was serviced. If interrupts 5.5 or 6.5 are masked off by bits D0 or D1, bits D4 and D5 will not be set. Bit D6, which corresponds to the 7.5 interrupt, will be set on to indicate that an interrupt was requested, even if it was masked off.
SERIAL INPUT DATA BIT D7: This bit provides the condition of the SID pin. It will be 1 if the pin is high, and 0 if it is low. The software examining this bit must have total ability to deal with whatever it finds there. The pin provides only a voltage level that exists at the time of the RIM execution.
When the RIM instruction is executed, the status of all the lines indicated are sampled, and the resulting bit pattern is placed in the A register. The instruction simply provides these conditions for display; it has no affect on the bits themselves. The bits in the A register may then be examined directly by logical instructions, or moved to a register or memory location for safekeeping.
SET INTERRUPT MASK (SIM): This instruction is the reverse of the RIM. While the RIM simply reads the status of various lines, the SIM sets various bits to form masks or generate output data via the SOD line. The conditions that the programmer wishes to set up must be set into the A register exactly as desired first, then the SIM Instruction is executed.
The SIM will take the bit pattern it finds in the A register and loads it into the masks in the following format:
D7
D6
D5
D4
D3
D2
D1
D0
SOD
S0E
X
R7.5
MSE
M7.5
M6.5
M5.5
RST MASKS BITS D0, D1, D2: These bits are the interrupt masks for the 5.5, 6.5, and 7.5 interrupts brought into the ‘85 on their own pins. The bits are 0 to enable and 1 to disable the interrupts. If bits D0 or D1 are disabled (set to 1), a signal applied to their respective pins cause no action. If D0 or D1 are set to 0 (enabled), their respective bits will be visible via the RIM instruction, and the call to the interrupt vector will occur. In the case of bit D2 for masking the 7.5 interrupt, the RIM instruction will indicate that a 7.5 interrupt is pending, but an automatic call will not occur.
MASK SET ENABLE BIT D3: This bit permits bits D0, D1, and D2 to be changed. If a SIM is executed with this bit low, the condition of the mask bits will not change. If a SIM is executed with this bit set high, the mask bits will take on the same arrangement as those given in the lower bits of the A register. This permits accessing of the mask byte to deal with the interrupts without affecting SOD.
RST 7.5 RESET BIT D4: This bit permits the SIM instruction to reset the interrupt pending flag indicated by bit D6 in the RIM instruction byte. Since the 7.5 interrupt is handled somewhat more importantly than the 5.5 and 6.5, it can indicate that it is pending via the RIM instruction even though it is masked off. This bit allows that pending request to be reset individually under program control.
UNDEFINED BIT D5: This bit is unused.
SOD ENABLE BIT D6: This bit works in conjunction with bit D7. If it is set to 1 when the SIM is executed, the condition of bit D7, high or low, is electrically loaded into the SOD latch, and in turn appears on the SOD pin of the ‘85. If bit D6 is low, the SIM’s execution has no affect on the bit D7. This, like bit D3, allows executing SIMs to service either interrupts or the serial I/O without affecting the other.
SERIAL OUTPUT DATA BIT D7: This bit contains the voltage level (+5 volts = 1, 0 volts = 0) which should appear at the SOD pin of the ‘85. If the SIM instruction is executed and bit D6 is set to 1 (enabled), the level contained by D7 is forwarded to the SOD latch, which will in turn cause it to appear on the SOD pin. If bit D6 is low, the SIM instruction will have no affect on bit D7.
The /RESET IN line affects the flags of the interrupt masks. First, the RST 7.5 latch which catches the rising edge of the 7.5 flip-flop and holds it for a RIM instruction is reset. Next, all three mask bits are set to a 1, which will disable all interrupts. Lastly, the SOD latch is reset to a 0. These will effectively allow the new instructions following the Reset to take full control of the MP, without interrupts causing immediate problems.
The use of these instructions will be explained under Interrupts in the "Additional Information" section of the notes.
ADDITIONAL INFORMATION
This section details several interesting items to round out the 8085 discussion. These include the Reset function, the expanded interrupt facilities, the SID and SOD lines, and additional support devices. Refer to the manual for details and further information.
RESET SYSTEM
The 8085 generates its own Reset function upon receipt of an asynchronous /RESET IN signal from an external source. This signal is probably generated from two sources, a Reset switch of some kind accessible to the operator, and a Power-on Reset circuit which causes a reset when power is applied to system. Receipt of /RESET IN is latched by an internal flip-flop at the rising edge of the next clock pulse (low asserted). At the beginning of the state following the latch of /RESET IN, RESET OUT is generated to the outside world, and the MP enters T-reset cycles. These cycles continue until the /RESET IN line is released. The release is sensed at the rising edge of the next clock pulse. This, in turn, allows the rising edge of the clock pulse following to enter a T1 state for the first instruction after reset.
The /RESET IN line should be held low for at least three T-states worth of time, to allow the ‘85 to fully synchronize itself and accomplish its tasks of resetting certain flip-flops and registers. Remember that the MP is very much alive during reset, and that it must have time in Reset mode to accomplish these tasks. The documentation mentions that certain of the control lines are tristated during reset, so that pull-up resistors are essential. When the /RESET IN line goes high, the MP will place the contents of the PC onto the address bus, and enter T1 of the M1 cycle for the next instruction. The PC was reset to all zeroes during the Reset cycle; therefore, the address appearing on the A0-A15 lines will be 0000H.
The Reset cycle does not affect the contents of any register except PC, or the arrangement of the condition flags. The Intel documentation indicates that the occurrence of Reset is essentially asynchronous with respect to the execution of the program in process. Therefore, the results of a Reset are undetermined, and not guaranteed.
The Reset cycle will reset, or turn off, the following items:
Program Counter
Instruction Register
Interrupt Enable FF
RST 7.5 FF
Trap FF
SOD FF
Machine State FF’s
Machine Cycle FF’s
Hold Internal FF
Interrupt Internal FF
Ready FF
The following items are turned on, or set, by the Reset cycle:
RST 5.5 Mask
RST 6.5 Mask
RST 7.5 Mask
Those items turned off, as listed above, will cause the MP to essentially become iS0lated from the possibilities of interrupts or any exterior interference until the new program, whatever was at 0000H, is underway. Turning on the mask bits effects the same thing, as these are on (set to 1) to disable the interrupts.
INTERRUPT FACILITIES
The 8085 contains three levels of interrupt capabilities. The first is essentially identical to that of the 8080 which technique it fully supports. The second technique involves the direct input pins 5.5, 6.5, and 7.5. These are maskable hardware interrupts. The third is Trap, which has its own pin and is non-maskable. Each will be discussed in detail.